Circuits for phase-cut analog dimming of solid state light sources

ABSTRACT

Circuits to provide phase-cut analog dimming of solid state light sources are presented. Each circuit comprises an anchoring circuit to communicate with a dimming controller circuit, the anchoring circuit having a proportional direct current (DC) voltage input, a biasing voltage input, a connection to a ground reference, and an output in communication with a dimming controller circuit. The anchoring circuit provides a reference voltage to permit phase cut dimming to be operable at a plurality of line voltages.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims is a continuation of, and claims priority to,U.S. patent application Ser. No. 14/681,823, now U.S. Pat. No. ______,entitled “CIRCUITS FOR PHASE-CUT ANALOG DIMMING OF SOLID STATE LIGHTSOURCES”, filed on Apr. 8, 2015, which claims the benefit of, andpriority to, U.S. Provisional Application No. 61/979,251, entitled“CIRCUIT FOR PHASE-CUT ANALOG DIMMING OF SOLID STATE LIGHT SOURCES”,filed on Apr. 14, 2014, and U.S. Provisional Application No. 62/078,184,entitled “PEAK DETECTOR TO ENABLE UNIVERSAL VOLTAGE PHASE CUT DIMMING”,filed on Nov. 11, 2014, the entire contents of all of which are herebyincorporated by reference.

TECHNICAL FIELD

The present invention relates to lighting, and more specifically, toelectronic drivers that power one or more solid state light sources.

BACKGROUND

Conventional wall dimmers work quite smoothly with traditional (e.g.,incandescent) lamp technology, and results in light that looks veryappealing. It is aesthetically pleasing and economical in itsimplementation. To be fully embraced by end users, this is the benchmarkdimming of solid state light sources needs to hit and then surpass.Unfortunately, dimmed solid state light sources often do not fare sowell. Substantial power savings alone do not overcome the desire of theend user who is looking to re-create the effect and response of theirexisting lighting infrastructure.

The two major types of phase-cut dimmers used today (so-called becausethey remove, or cut, selected portions from each AC half-cycle wave) areleading-edge dimmers (LEDIM) and trailing-edge dimmers (TEDIM).

Consider an environment such as restaurants. Restaurants arequintessential environments for dimmer use, with the business norm beingthat lighting is in some dimmed mode, usually within the bottom 20% ofthe full-light level, to create a traditional intimate diningexperience. By varying dimming, restaurants create areas of highluminance contrast ratios by having a low level background light betweentables with often a highlight lamp or central candle placed on the tableto create pools of lighting. After closing, and during the day, therestaurant may also require 100% lighting levels for cleaning, next daypreparations, and so on. Movie theaters are another example of anenvironment where lighting is required in both dimmed mode (during theshowing of a movie) and high luminance (non-dimmed) mode (before andafter the movie is shown).

SUMMARY

Conventional techniques for dimming solid state light sources usuallyinvolve complicated circuitry to work with a traditional phase-cutdimmer or simply bypass or require the removal of a traditionalphase-cut dimmer. Thus, there is currently no solution in particular forphase-cut dimming at 277 VAC applied to an analog primary-side regulatedfly-back topology. Some analog solid state light source power supplieshaving universal input voltage capability (120 VAC and 277 VAC) may needphase-cut dimming (PCD) at 277 VAC, especially in retrofit applications.A primary-side regulated analog fly-back converter, in which themultiplier pin of the controller has to be conditioned to make theconverter respond properly to either 120V or 277V, can operate withuniversal input voltage, but PCD is only suitable at 120V. Embodimentsdescribed herein solve the above mentioned problem, by introducing acircuit that enables the analog converter to be properly dimmed at 277Vas well as 120V.

In an embodiment, there is provided a circuit. The circuit includes ananchoring circuit in communication with a dimming controller circuit,the anchoring circuit including a proportional direct current (DC)voltage input, a biasing voltage input, a connection to a groundreference, and an output in communication with the dimming controllercircuit; wherein the anchoring circuit provides a reference voltage topermit phase cut dimming to be operable at a plurality of line voltages.

In a related embodiment, the anchoring circuit may include a firstresistor including a first lead coupled to a positive proportional DCvoltage and including a second lead; a second resistor including a firstlead coupled to a biasing voltage and including a second lead; a thirdresistor including a first lead coupled to the biasing voltage andincluding a second lead; a fourth resistor including a first leadcoupled to the second lead of the second resistor and including a secondlead; a fifth resistor including a first lead coupled to a second leadof the third resistor and including a second lead; a first transistorincluding a first lead coupled to the second lead of the secondresistor, a second lead coupled to the second lead of the firstresistor, and a third lead coupled to the ground reference; a secondtransistor including a first lead coupled to the second lead of thefourth resistor, a second lead coupled to the second lead of the thirdresistor, and a third lead coupled to the ground reference; and a thirdtransistor including a first lead coupled to the second lead of thefifth resistor, a second lead including an output of the anchoringcircuit, and a third lead coupled to the ground reference.

In a further related embodiment, the first transistor may include asilicon controlled rectifier (SCR) and the first lead of the SCR mayinclude an anode, the second lead may include a gate, and the third leadmay include a cathode. In another further related embodiment, the secondtransistor may include an NPN transistor and the first lead of the NPNtransistor may include a base of the NPN transistor, the second lead mayinclude an emitter of the NPN transistor, and the third lead may includea collector of the NPN transistor. In still another further relatedembodiment, the third transistor may include a MOSFET and the first leadof the MOSFET may include a gate of the MOSFET, the second lead mayinclude a drain of the MOSFET, and the third lead may include a sourceof the MOSFET.

In yet another further related embodiment, for a first input voltage thethird transistor may be open, the second transistor may be closed, andthe first transistor may be open. In still yet another further relatedembodiment, for a second input voltage the third transistor may beclosed, the second transistor may be open, and the first transistor maybe closed.

In another related embodiment, the anchoring circuit may include: afirst resistor comprising a first lead coupled to a line voltage andcomprising a second lead; a second resistor comprising a first leadcoupled to a second lead of the first resistor and comprising a secondlead coupled to the ground reference; a diode comprising a first leadcomprising an anode coupled to the second lead of the first resistor andcomprising a second lead comprising a cathode; a third resistorcomprising a first lead coupled to the second lead of the diode andcomprising a second lead; a fourth resistor comprising a first leadcoupled to the second lead of the third resistor and comprising a secondlead coupled to the ground reference; a first capacitor comprising afirst lead coupled to the second lead of the diode, and comprising asecond lead coupled to the ground reference; a first transistorcomprising a first lead coupled to the second lead of the fourthresistor, a second lead comprising an output of the anchoring circuit,and a third lead coupled to the ground reference; and a second capacitorcomprising a first lead coupled to the second lead of the firsttransistor, and comprising a second lead capable of being coupled to thedimming controller circuit.

In a further related embodiment, the first transistor may include aMOSFET and wherein the first lead of the MOSFET may include a gate ofthe MOSFET, the second lead may include a drain of the MOSFET, and thethird lead may include a source of the MOSFET.

In another embodiment, there is provided a phase cut dimming circuit.The phase cut dimming circuit includes: a dimming controller circuit,the dimming controller circuit comprising an input receiving a linevoltage, a connection to a ground, and an output; an anchoring circuitin communication with the dimming controller circuit, the anchoringcircuit comprising an input, a connection to a ground, and an output incommunication with the dimming controller circuit; wherein the anchoringcircuit provides a reference voltage to permit phase cut dimming to beoperable at a plurality of line voltages.

In a related embodiment, the dimming controller circuit may include acontroller comprising an input coupled to a center point of a voltagedivider circuit, the controller providing an output to couple to aprimary side regulated analog flyback converter; and a voltage dividercircuit coupled between the line voltage and the ground, wherein thevoltage divider circuit may include: a first resistor comprising a firstlead coupled to the input of the controller and a second lead coupled tothe ground; a second resistor comprising a first lead coupled to theinput of the controller and a second lead coupled to the line voltage,and wherein the first lead of the second resistor and the first lead ofthe first resistor comprise the center point of the voltage dividercircuit; and a third resistor comprising a first lead coupled to thecenter point of the voltage divider circuit and a second lead to coupleto an input of the anchoring circuit.

In another related embodiment, the anchoring circuit may include: afirst resistor comprising a first lead coupled to a positiveproportional DC voltage and comprising a second lead; a second resistorcomprising a first lead coupled to a biasing voltage and comprising asecond lead; a third resistor comprising a first lead coupled to thebiasing voltage and comprising a second lead; a fourth resistorcomprising a first lead coupled to the second lead of the secondresistor and comprising a second lead; a fifth resistor comprising afirst lead coupled to a second lead of the third resistor and comprisinga second lead; a first transistor comprising a first lead coupled to thesecond lead of the second resistor, a second lead coupled to the secondlead of the first resistor, and a third lead coupled to the groundreference; a second transistor comprising a first lead coupled to thesecond lead of the fourth resistor, a second lead coupled to the secondlead of the third resistor, and a third lead coupled to the groundreference; and a third transistor comprising a first lead coupled to thesecond lead of the fifth resistor, a second lead comprising an output ofthe anchoring circuit, and a third lead coupled to the ground reference.In a further related embodiment, the first transistor may include asilicon controlled rectifier (SCR) and the first lead of the SCR mayinclude an anode, the second lead may include a gate, and the third leadmay include a cathode.

In another further related embodiment, the second transistor may includean NPN transistor and the first lead of the NPN transistor may include abase of the NPN transistor, the second lead may include an emitter ofthe NPN transistor, and the third lead may include a collector of theNPN transistor. In yet another further related embodiment, the thirdtransistor may include a MOSFET and wherein the first lead of the MOSFETmay include a gate of the MOSFET, the second lead may include a drain ofthe MOSFET, and the third lead may include a source of the MOSFET.

In still another further related embodiment, for a first input voltage,the third transistor may be open, the second transistor may be closed,and the first transistor may be open. In yet still another furtherrelated embodiment, for a second input voltage, the third transistor maybe closed, the second transistor may be open, and the first transistormay be closed.

In still yet another further related embodiment, the anchoring circuitmay include: a first resistor comprising a first lead coupled to a linevoltage and comprising a second lead; a second resistor comprising afirst lead coupled to a second lead of the first resistor and comprisinga second lead coupled to the ground reference; a diode comprising afirst lead comprising an anode coupled to the second lead of the firstresistor and comprising a second lead comprising a cathode; a thirdresistor comprising a first lead coupled to the second lead of the diodeand comprising a second lead; a fourth resistor comprising a first leadcoupled to the second lead of the third resistor and comprising a secondlead coupled to the ground reference; a first capacitor comprising afirst lead coupled to the second lead of the diode, and comprising asecond lead coupled to the ground reference; a first transistorcomprising a first lead coupled to the second lead of the fourthresistor, a second lead comprising an output of the anchoring circuit,and a third lead coupled to the ground reference; and a second capacitorcomprising a first lead coupled to the second lead of the firsttransistor, and comprising a second lead capable of being coupled to thedimming controller circuit.

In a further related embodiment, the first transistor may include aMOSFET and wherein the first lead of the MOSFET may include a gate ofthe MOSFET, the second lead may include a drain of the MOSFET, and thethird lead may include a source of the MOSFET.

Note that each of the different features, techniques, configurations,etc. discussed herein can be executed independently or in combination.Accordingly, the present invention can be embodied and viewed in manydifferent ways. Also, note that this summary section herein does notspecify every embodiment and/or incrementally novel aspect of thepresent disclosure or claimed invention. Instead, this summary onlyprovides a preliminary discussion of different embodiments andcorresponding points of novelty over conventional techniques. Foradditional details, elements, and/or possible perspectives(permutations) of the invention, the reader is directed to the DetailedDescription section and the corresponding figures as further discussedbelow.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other objects, features and advantages disclosedherein will be apparent from the following description of particularembodiments disclosed herein, as illustrated in the accompanyingdrawings in which like reference characters refer to the same partsthroughout the different views. The drawings are not necessarily toscale, emphasis instead being placed upon illustrating the principlesdisclosed herein.

FIG. 1 depicts a schematic of a conventional controller and supportcircuitry for handling a single line voltage.

FIG. 2 depicts a schematic of a conventional controller and supportcircuitry for handling multiple line voltages.

FIG. 3 depicts a graph of the voltage and power provided by the circuitof FIG. 2.

FIG. 4 depicts a graph showing a dimming range for a first line voltage.

FIG. 5 depicts a graph showing a dimming range for a second linevoltage.

FIG. 6 depicts a schematic of another conventional controller andsupport circuitry for handling multiple line voltages.

FIG. 7 depicts a graph of the voltage and current provided by thecircuit of FIG. 6.

FIG. 8 depicts a graph showing a dimming range for a first line voltagefor the circuit of FIG. 6.

FIG. 9 depicts a graph showing a dimming range for a second line voltagefor the circuit of FIG. 6.

FIG. 10 depicts a schematic of a first circuit to provide phase-cutanalog dimming of solid state light sources according to embodimentsdisclosed herein.

FIG. 11 depicts a graph showing a dimming range for multiple linevoltages for the circuit of FIG. 10, according to embodiments disclosedherein.

FIG. 12 depicts a schematic of the first circuit to provide phase-cutanalog dimming of solid state light sources including an anchoringcircuit according to embodiments disclosed herein.

FIG. 13 depicts a schematic of a second circuit to provide phase-cutanalog dimming of solid state light sources according to embodimentsdisclosed herein.

FIG. 14 depicts a graph showing a dimmer at minimum light in a trailingedge mode according to embodiments disclosed herein.

FIG. 15 depicts a graph showing a dimmer at minimum light in a leadingedge mode according to embodiments disclosed herein.

DETAILED DESCRIPTION

The embodiments set forth below represent the necessary information toenable those skilled in the art to practice the invention and illustratethe best mode of practicing embodiments of the invention. Upon readingthe following description in light of the accompanying figures, thoseskilled in the art will understand the concepts of the invention andrecognize applications of these concepts not particularly addressedherein. It should be understood that these concepts and applicationsfall within the scope of the disclosure and the accompanying claims.

Embodiments shown and described throughout allow analog primary-sideregulated fly-back converters to be upgraded to enable phase cut dimmingat, for example, 277 VAC, by using a low cost analog anchoring circuit.The circuit enables a linear range of clean dimming for solid statelight sources. Referring to FIG. 1, a dedicated voltage (either 120 or277 Volts Alternating Current (VAC)) configuration 10 is shown in whicha voltage V₁ at a multiplier pin MULT of a controller U1 is simply takenfrom a voltage-divider of a line voltage V_(line), given byV₁=V_(line)R1/(R1+R2). Using this configuration, phase-cut dimming ispossible, but not for universal voltage operation. That is, a change inthe line voltage V_(line) results in corresponding changes required inthe first resistor R1, which has a first lead and a second lead, and thesecond resistor R2, which also has a first lead and a second lead. Thefirst lead of the second resistor R2 is connected to the line voltageV_(line), and the second lead of the second resistor R2 is connected tothe first lead of the first resistor R1. The second lead of the firstresistor R1 is connected to ground.

When universal input voltage operation is needed, a modified circuit 20including extra circuitry than shown in FIG. 1 is required around themultiplier pin MULT of the controller U1, like the one shown in FIG. 2,in order to make the circuit 20 deliver the same level of power at both120 VAC and 277 VAC. Here, the line voltage V_(line) appears in the formof a proportional direct current (DC) voltage V₄ at an input of avoltage-to-current device, which is actually an NPN transistor, with aninput current i₃ being a collector current. The collector of the NPNtransistor (i.e., the voltage-to-current device) is connected to a thirdresistor R3, which is connected to the voltage divider formed by thefirst resistor R1 and the second resistor R2. More specifically, thethird resistor R3 has a first lead, connected to the collector of theNPN transistor, and a second lead, connected to the voltage divider(i.e., to the second lead of the second resistor R2 and the first leadof the first resistor R1). A capacitor C1, having a first lead and asecond lead, is in parallel across the first resistor R1, such that thefirst lead of the capacitor C1 is connected to the first lead of thefirst resistor R1, and the second lead of the capacitor C1 is connectedto the second lead of the first resistor R1. At 120 VAC, with nodimming, the proportional DC voltage V₄ is relatively low and drives theNPN transistor into cut-off, so the voltage V₁ at the multiplier pinMULT follows the voltage-divider effect given by the selected firstresistor R1 and the second resistor R2. At 277 VAC, with no dimming, theproportional DC voltage V₄ goes high, the NPN transistor enters itsactive region, and the collector current i₃ increases, pulling thevoltage V₁ down in such a way that output power remains the same as at120 VAC. This is illustrated in a graph 30 shown in FIG. 3. Allcomponent values are tuned to give the same output power duringno-dimming operation at both points A and B in the graph 30.

When phase-cut dimming is performed at 120 VAC, the proportional DCvoltage V₄ decreases when the dimmer is slid down. This does not affectthe situation with the voltage V₁, as the NPN transistor remains incut-off, so the third resistor R3 between the voltage divider and theNPN transistor (shown in FIG. 2) is not in the circuit. The output powergoes with the dimmer action, from 0V to point A, and the voltage V₁remains at the same level in at point A as shown in a graph 40 of FIG.4. However, if the same circuit is used for phase-cut dimming at 277VAC, no linearity shows up between the output light and the dimmerposition, from 0V to point B, as illustrated in a graph 50 of FIG. 5.Therefore, the circuit of FIG. 2 is not recommended for 277 VACphase-cut dimming purposes, as it produces non-linear results.

Referring now to FIG. 6, a circuit 60 is shown that allows a properresponse of the converter for universal input voltage. When operating ata first voltage, for example 120 VAC, a switch Q1 (which in someembodiments is a MOSFET) is maintained open, in which case the voltageV₁ at the multiplier pin MULT of the controller U1 is taken from astraightforward voltage divider of the rectified line voltage V_(line),given by V₁=V_(line)*R1/(R1+R2). A capacitor C1 is present to reducenoise at the multiplier pin MULT. When operating at a second voltage,for example 277 VAC, the switch Q1 should be maintained closed. Thisplaces the first resistor R1 in parallel with the third resistor R3,which furnishes a lower voltage V₁, making the circuit deliver justabout the same output current as at the first voltage (e.g., 120 VAC),as shown in FIG. 7, which is a graph 70 of the voltage V₁ at themultiplier pin MULT and an output current I_(out) at 120 VAC and 277 VACoperation. A second capacitor C2, in parallel with the capacitor C1,reinforces the bypass action at the multiplier pin MULT.

Looking again at the graph 70 of FIG. 7 when dimming is applied, thebehavior of the output current I_(out) versus the dimmer position is notthe same for dimming at the first voltage (i.e., 120 VAC) as for dimmingat the second voltage (i.e., 277 VAC). When a dimmer is connected at thefirst voltage (i.e., 120 VAC), the output current I_(out) willsubstantially follow the position of the dimmer. But when dimming occursat the second voltage (i.e., 277 VAC), there is a challenge of theoutput current I_(out) going high, which occurs somewhere in between 120VAC and 277 VAC, possibly around the midway point, resulting in an“overlight” situation. Graphs 80 and 90 of FIGS. 8 and 9, respectively,illustrate the situation comparing the output current I_(out) for 120VAC dimming (FIG. 8) with 277 VAC dimming (FIG. 9). FIG. 9 also showswhat the desired behavior of the output current I_(out) at 277 VACdimming should be. Embodiments make the desired behavior happen whenphase-cut dimming occurs at the second voltage (e.g., 277 VAC), withoutgoing into the unwanted “overlight” situation.

The presently disclosed circuits for phase-cut analog dimming of solidstate light sources allow the primary-side regulated power supply to becompatible with leading edge and trailing edge dimmers for both 120 VACand 277 VAC. FIG. 10 shows a circuit 100, which is substantially similarto the circuit 20 of FIG. 2, except that the NPN transistor is replacedwith an anchoring circuit 110, such that the first lead of the thirdresistor R3 is connected to the anchoring circuit 110. At 120 VAC, theanchoring circuit 110 makes the third resistor R3 to be out of thecircuit (such that the current i₃=0, or a voltage between the anchoringcircuit 110 and the third resistor R3 V₃=the voltage V₁, which is at ahigh level), and stays like that during the whole sliding range of thephase-cut dimmer. At 277 VAC, the anchoring circuit makes the thirdresistor R3 to be in the circuit (that is, the voltage V₃≈0), so thevoltage V1 is at a low level, and stays like that for the whole slidingrange of the 277 V dimmer. This allows the phase cut dimming at 277 VACto be done in such a way that the output current, and thus the lightoutput by the solid state light source(s) driven by that output current,goes with the dimmer action, as illustrated in a graph 111 shown in FIG.11.

A schematic of a circuit 120 including the anchoring circuit 110 indetail and the rest of the circuit 100 of FIG. 10 is shown in FIG. 12. AMOSFET Q3 having three leads, that is, a gate, a source, and a drain, isconnected between the third resistor R3 and ground. More specifically,the source is connected to the first lead of the third resistor R3, thedrain is connected to ground, and the gate is connected to a fourthresistor R4. The fourth resistor R4 has a first lead, which is connectedto a fifth resistor R5, and a second lead, which is connected to thegate of the MOSFET Q3. The fifth resistor R5 has a first lead and asecond lead, where the second lead is connected to the first lead of thefourth resistor R4 and to an NPN transistor Q2 having three leads, thatis, a base, a collector, and an emitter. More specifically, the secondlead of the fifth resistor R5 and the first lead of the fourth resistorR4 are connected to the collector of the NPN transistor Q2. The emitterof the NPN transistor Q2 is connected to ground. The base of the NPNtransistor Q2 is connected to a sixth resistor R6, which has a firstlead and a second lead. The second lead of the sixth resistor R6 isconnected to the base of the NPN transistor Q2, while the first lead ofthe sixth resistor R6 is connected to a seventh resistor R7. The seventhresistor R7 has a first lead, which is connected to the first lead ofthe sixth resistor R6, and a second lead, which is connected to thefirst lead of the fifth resistor R5. The sixth resistor R6 and theseventh resistor R7 are each connected to a silicon controller rectifierQ1, which has three leads, that is, an anode, a gate, and a cathode.Thus, the first lead of the sixth resistor R6 and the first lead of theseventh resistor R7 are both connected to the anode of the siliconcontroller rectifier Q1. The cathode of the silicon controller rectifierQ1 is connected to ground, and the gate of the silicon controllerrectifier Q1 is connected to an eighth resistor R8. The eighth resistorR8 has a first lead, connected to the proportional DC voltage V₄, and asecond lead, connected to the gate of the silicon controller rectifierQ1.

In order to differentiate between operating and dimming at 120 VAC incomparison with operating and dimming at 277 VAC, the following happens.The MOSFET Q3 is open when the circuit 120 normally operates at 120 VAC,and along the whole sliding range of the phase-cut dimmer at 120 VAC.During all these events, the NPN transistor Q2 remains closed, and thesilicon controller rectifier Q1 remains open. The MOSFET Q3 is closedwhen the circuit 120 is powered with 277 VAC, and along the wholesliding range of the phase-cut dimmer at 277 VAC. During all theseevents, the NPN transistor Q2 remains open, and the silicon controllerrectifier Q1 remains closed.

This is summarized in Table 1. To make these conditions happen, theaction of the silicon controller rectifier (SCR) Q1 has to be set bychoosing the values of the seventh resistor R7 and the eighth resistorR8 in such a way that the silicon controller rectifier Q1 triggers at277 VAC, but not at 120 VAC. In addition, a biasing voltage V′_(cc),applied to the first lead of the fifth resistor R5 and the second leadof the seventh resistor R7, is incorporated to maintain the status ofthe silicon controller rectifier Q1, the NPN transistor Q2, and theMOSFET Q3, as required. To avoid loading problems at turn-on, thebiasing voltage V′_(cc) is separated from a regular voltage V_(cc)assigned to a microcontroller U1, being both originated from the sameauxiliary winding in a transformer (not shown).

TABLE 1 State of switches during full range of dimming V_(line) Q₁ Q₂ Q₃PCD 120 VAC open close open Whole range 277 VAC close open close Wholerange

FIG. 13 shows a circuit 130 to allow a proper response to phase-cutdimming for universal input voltage. The circuit 130 includes thecontroller U1, with the multiplier pin MULT, connected to a voltagedivider formed by the first resistor R1 and the second resistor R2, withthe voltage V₁ and the line voltage V_(line), and the third resistor R3and the capacitor C1 all connected as described above. The circuit 130also includes a second capacitor C2 having a first lead and a secondlead, with the first lead connected to the first lead of the thirdresistor R3 and the second lead connected to the second lead of thethird resistor R3, such that the second capacitor C2 is in parallel withthe third resistor R3. The circuit 130 also includes a MOSFET Q4, havingthree leads, that is, a gate, a source, and a drain. The source isconnected to the first lead of the third resistor R3 and the first leadof the second capacitor C2. The drain is connected to ground, and thegate is connected to the fourth resistor R4 and the fifth resistor R5.The fourth resistor R4 and the fifth resistor R5 each have a first leadand a second lead, where the second lead of the fourth resistor R4 isconnected to the first lead of the fifth resistor R5, and both areconnected to the gate of the MOSFET Q4. The second lead of the fifthresistor R5 is connected to ground. The first lead of the fourthresistor R4 is connected to a first lead of a third capacitor C3, whichalso has a second lead connected to ground. Thus, the third capacitor C3is in parallel with the series connection of the fourth resistor R4 andthe fifth resistor R5. The first lead of the fourth resistor R4 is alsoconnected to a diode D1, which has two leads, that is, an anode and acathode. The cathode of the diode D1 is connected to the first lead ofthe fourth resistor R4 and the first lead of the third capacitor C3. Theanode of the diode D1 is connected to the sixth resistor R6, which has afirst lead and a second lead, and to the seventh resistor R7, which hasa first lead and a second lead. The first lead of the seventh resistorR7 is connected to the anode of the diode D1, and the second lead of theseventh resistor R7 is connected to ground. The first lead of the sixthresistor R6 is connected to the anode of the diode D1 and the secondlead of the sixth resistor R6 is connected to the line voltage V_(line).

When operating at a first voltage, for example 120 VAC, the MOSFET Q4 ismaintained open, in which case the voltage V₁ at the multiplier pin MULTof the controller U1 is taken from a straightforward voltage divider ofthe rectified line voltage, given by V₁=V_(line)*R1/(R1+R2). Thecapacitor C1 is present to reduce noise at the multiplier pin MULT. Whenoperating at a second voltage, for example 277 VAC, the MOSFET Q4 ismaintained closed, placing the first resistor R1 in parallel with thethird resistor R3, which results in a lower voltage V₁, making thecircuit 130 deliver just about the same output current as when operatingat the first voltage (e.g., 120 VAC). The second capacitor C2 is alsonow in parallel with the capacitor C1, which reinforces the bypassaction at the multiplier pin MULT. The third capacitor C3 is of a value(for example, ˜1 μF) in order to be always charged in one directionthrough the diode D1 up to a voltage V_(P), which is proportional to thepeak voltage detected from the rectified line voltage V_(line). TheMOSFET Q4 turns on or off, according to the value of the voltage V_(P).When operating with no dimmer at a first voltage (e.g., 120V), thevoltage V_(P) will be proportional to a first peak value (e.g., 17 V).When operating with no dimmer at a second voltage (e.g., 277V), thevoltage V_(P) will be proportional to a second peak value (e.g., 392 V).In consequence, resistance ratios R7/(R6+R7) and R5/(R4+R5) are selectedin such a way that at the first voltage (e.g., 120V), the MOSFET Q4 iscontinuously open, and at the second voltage (e.v., 277V), the MOSFET Q4is continuously closed.

In addition, the resistance ratios R7/(R6+R7) and R5/(R4+R5) have tomeet another important condition. When a phase-cut dimmer/phase cutdimming circuitry is connected to the circuit 130, for any possibleinput voltage, along any position of the dimmer, and using eithertrailing-edge or leading-edge mechanism, the gate voltage at the MOSFETQ4 should be in such a way that the MOSFET Q4 will unambiguously eithercontinuously open during dimming at the first voltage or continuouslyclose during dimming at the second voltage. This unambiguousness of thevoltage V_(P) should occur even at the minimum position of the dimmer,which usually is not less than 30° in commercially available cut-phasedimmers.

FIGS. 14 and 15 show graphs 140, 150 of the state of switches over therange of dimming. The graphs 140, 150 show that, for both leading-edge(the graph 140) and trailing-edge (the graph 150) operation, thedetectable peak value for the first voltage (e.g., 120V) goes from afirst value (e.g., 85V) up to a second value (e.g., 170V), and for thesecond voltage (e.g., 277V), the detectable peak goes from a third value(e.g., 196V) up to a fourth value (e.g., 392V). This means that thelowest detectable peak at dimming at the second voltage will always behigher than the second value. Therefore, selecting the resistance ratiosas, for example, R7/(R6+R7)=0.03 and R˜(R4+R5)=0.96, assures anunmistaken operation during any phase cut dimming. Thus, embodimentssuch as shown in FIG. 13 provide a simple, low-cost configuration toenable the driver to perform reliable operation during dimming atmultiple input voltages, such as but not limited to both 120V and 277V.

Unless otherwise stated, use of the word “substantially” may beconstrued to include a precise relationship, condition, arrangement,orientation, and/or other characteristic, and deviations thereof asunderstood by one of ordinary skill in the art, to the extent that suchdeviations do not materially affect the disclosed methods and systems.

Throughout the entirety of the present disclosure, use of the articles“a” and/or “an” and/or “the” to modify a noun may be understood to beused for convenience and to include one, or more than one, of themodified noun, unless otherwise specifically stated. The terms“comprising”, “including” and “having” are intended to be inclusive andmean that there may be additional elements other than the listedelements.

Elements, components, modules, and/or parts thereof that are describedand/or otherwise portrayed through the figures to communicate with, beassociated with, and/or be based on, something else, may be understoodto so communicate, be associated with, and or be based on in a directand/or indirect manner, unless otherwise stipulated herein.

Although the methods and systems have been described relative to aspecific embodiment thereof, they are not so limited. Obviously manymodifications and variations may become apparent in light of the aboveteachings. Many additional changes in the details, materials, andarrangement of parts, herein described and illustrated, may be made bythose skilled in the art.

What is claimed is:
 1. An anchoring circuit in communication with adimming controller circuit, comprising: a proportional direct current(DC) voltage input; a biasing voltage input; a connection to a groundreference; a first resistor comprising a first lead and a second lead,wherein the first lead of the first resistor is coupled to a linevoltage; a second resistor comprising a first lead and a second lead,wherein the first lead of the second resistor is coupled to the secondlead of the first resistor, and wherein the second lead of the secondresistor is coupled to connection to the ground reference; a diodecomprising an anode and a cathode, wherein the anode is coupled to thesecond lead of the first resistor; a first capacitor comprising a firstlead and a second lead, wherein the first lead of the first capacitor iscoupled to the cathode of the diode, and wherein the second lead of thefirst capacitor is coupled to the connection to the ground reference; athird resistor comprising a first lead and a second lead, wherein thefirst lead of the third resistor is coupled to the cathode of the diode;a fourth resistor comprising a first lead and a second lead, wherein thefirst lead of the fourth resistor is coupled to the second lead of thethird resistor, and wherein the second lead of the fourth resistor iscoupled to the connection to the ground reference; a first transistorcomprising a first lead, a second lead, and a third lead, wherein thefirst lead of the first transistor is coupled to the second lead of thefourth resistor, wherein the third lead of the first transistor iscoupled to the connection to the ground reference, and wherein thesecond lead of the first transistor comprises an output of the anchoringcircuit in communication with the dimming controller circuit; a fifthresistor comprising a first lead and a second lead, wherein the firstlead of the fifth resistor is coupled to the second lead of the thirdresistor; a second transistor comprising a first lead, a second lead,and a third lead, wherein the first lead of the second transistor iscoupled to the second lead of the fourth resistor, wherein the secondlead of the second transistor is coupled to the second lead of the thirdresistor, and wherein the third lead of the second transistor is coupledto the connection to the ground reference; a third transistor comprisinga first lead, a second lead, and a third lead, wherein the first lead ofthe third transistor is coupled to the second lead of the fifthresistor, and wherein the third lead of the first transistor is coupledto the connection to the ground reference; and a second capacitorcomprising a first lead and a second lead, wherein the first lead of thesecond capacitor is coupled to the second lead of the first transistor,and the second lead of the second capacitor is capable of being coupledto the dimming controller circuit; wherein the anchoring circuitprovides a reference voltage to permit phase cut dimming to be operableat a plurality of line voltages.
 2. The anchoring circuit of claim 1,wherein the first transistor comprises a MOSFET and wherein the firstlead of the MOSFET comprises a gate of the MOSFET, the second lead ofthe MOSFET comprises a drain of the MOSFET, and the third lead of theMOSFET comprises a source of the MOSFET.
 3. The anchoring circuit ofclaim 1, wherein the first transistor comprises a silicon controlledrectifier (SCR) and wherein the first lead of the SCR comprises ananode, the second lead comprises a gate, and the third lead comprises acathode.
 4. The anchoring circuit of claim 1, wherein the secondtransistor comprises an NPN transistor and wherein the first lead of theNPN transistor comprises a base of the NPN transistor, the second leadof the NPN transistor comprises an emitter of the NPN transistor, andthe third lead of the NPN transistor comprises a collector of the NPNtransistor.
 5. The anchoring circuit of claim 1, wherein the thirdtransistor comprises a MOSFET and wherein the first lead of the MOSFETcomprises a gate of the MOSFET, the second lead of the MOSFET comprisesa drain of the MOSFET, and the third lead of the MOSFET comprises asource of the MOSFET.
 6. The anchoring circuit of claim 1, wherein for afirst input voltage, the third transistor is open, the second transistoris closed, and the first transistor is open.
 7. The anchoring circuit ofclaim 1, wherein for a second input voltage, the third transistor isclosed, the second transistor is open, and the first transistor isclosed.
 8. A phase cut dimming circuit, comprising: a dimming controllercircuit comprising an input configured to receive a line voltage, aconnection to a ground, and an output; an anchoring circuit incommunication with the dimming controller circuit, the anchoring circuitcomprising an input, a connection to a ground, and an output incommunication with the dimming controller circuit; wherein the anchoringcircuit provides a reference voltage to permit phase cut dimming to beoperable at a plurality of line voltages, and wherein the anchoringcircuit comprises: a first resistor comprising a first lead and a secondlead, wherein the first lead of the first resistor is coupled to a linevoltage; a second resistor comprising a first lead and a second lead,wherein the first lead of the second resistor is coupled to the secondlead of the first resistor, and the second lead of the second resistoris coupled to a ground; a diode comprising an anode and a cathode,wherein the anode is coupled to the second lead of the first resistor; afirst capacitor comprising a first lead and a second lead, wherein thefirst lead of the first capacitor is coupled to the cathode of thediode, and wherein the second lead of the first capacitor is coupled toa ground; a third resistor comprising a first lead and a second lead,wherein the first lead of the third resistor is coupled to the cathodeof the diode; a fourth resistor comprising a first lead and a secondlead, wherein the first lead of the fourth resistor is coupled to thesecond lead of the third resistor, and wherein the second lead of thefourth resistor is coupled to a ground; a first transistor comprising afirst lead, a second lead, and a third lead, wherein the first lead ofthe first transistor is coupled to the second lead of the fourthresistor, wherein the third lead of the first transistor is coupled to aground, and wherein the second lead of the first transistor comprises anoutput of the anchoring circuit in communication with the dimmingcontroller circuit; a fifth resistor comprising a first lead and asecond lead, wherein the first lead of the fifth resistor is coupled tothe second lead of the third resistor; a second transistor comprising afirst lead, a second lead, and a third lead, wherein the first lead ofthe second transistor is coupled to the second lead of the fourthresistor, wherein the second lead of the second transistor is coupled tothe second lead of the third resistor, and wherein the third lead of thesecond transistor is coupled to a ground; a third transistor comprisinga first lead, a second lead, and a third lead, wherein the first lead ofthe third transistor is coupled to the second lead of the fifthresistor, and wherein the third lead of the first transistor is coupledto the connection to a ground; and a second capacitor comprising a firstlead and a second lead, wherein the first lead of the second capacitoris coupled to the second lead of the first transistor, and the secondlead of the second capacitor is capable of being coupled to the dimmingcontroller circuit
 9. The phase cut dimming circuit of claim 8, whereinthe first transistor comprises a MOSFET and wherein the first lead ofthe MOSFET comprises a gate of the MOSFET, the second lead of the MOSFETcomprises a drain of the MOSFET, and the third lead of the MOSFETcomprises a source of the MOSFET.
 10. The phase cut dimming circuit ofclaim 8, wherein the dimming controller circuit comprises: a controllercomprising an input coupled to a center point of a voltage dividercircuit, the controller providing an output to couple to a primary sideregulated analog flyback converter; and wherein the voltage dividercircuit is coupled between the line voltage and a ground, and whereinthe voltage divider circuit comprises: a first resistor comprising afirst lead coupled to the input of the controller and a second leadcoupled to the ground; a second resistor comprising a first lead coupledto the input of the controller and a second lead coupled to the linevoltage, and wherein the first lead of the second resistor and the firstlead of the first resistor comprise the center point of the voltagedivider circuit; and a third resistor comprising a first lead coupled tothe center point of the voltage divider circuit and a second lead tocouple to an input of the anchoring circuit.
 11. The phase cut dimmingcircuit of claim 8, wherein the first transistor comprises a siliconcontrolled rectifier (SCR) and wherein the first lead of the SCRcomprises an anode, the second lead of the SCR comprises a gate, and thethird lead of the SCR comprises a cathode.
 12. The phase cut dimmingcircuit of claim 8, wherein the second transistor comprises an NPNtransistor and wherein the first lead of the NPN transistor comprises abase of the NPN transistor, the second lead of the NPN transistorcomprises an emitter of the NPN transistor, and the third lead of theNPN transistor comprises a collector of the NPN transistor.
 13. Thephase cut dimming circuit of claim 8, wherein the third transistorcomprises a MOSFET and wherein the first lead of the MOSFET comprises agate of the MOSFET, the second lead of the MOSFET comprises a drain ofthe MOSFET, and the third lead of the MOSFET comprises a source of theMOSFET.
 14. The phase cut dimming circuit of claim 8, wherein for afirst input voltage, the third transistor is open, the second transistoris closed, and the first transistor is open.
 15. The phase cut dimmingcircuit of claim 8, wherein for a second input voltage, the thirdtransistor is closed, the second transistor is open, and the firsttransistor is closed.